1. Field of the Invention
The present invention relates generally to semiconductor devices and the manufacturing method thereof, and particularly to a structure of memory cells of a dynamic random access memory (referred to as DRAM hereinafter) and the manufacturing method thereof.
2. Description of the Background Art
The process of forming the memory cells of a conventional DRAM will be partially described by referring to FIGS. 1A to 1D.
An element isolation region 2 for isolating and insulating active regions is formed on the surface of a semiconductor substrate 1, at least the active region of which is of p type, by a so-called LOCOS (LOCal Oxidation of Silicon) method (FIG. 1A).
On the semiconductor substrate 1, sequentially formed are a gate insulating film 3, a polysilicon layer 4 doped with impurities and an insulating layer 5, and those are selectively removed by photolithography and etching to pattern gate electrodes 6a, 6b, 6c and 6d. Then, using the gate electrodes 6a, 6b, 6c and 6d as masks, n type impurity ions are implanted into active regions on the surface of the semiconductor substrate to form low concentrated n type impurity regions 7. An oxide insulating film having a prescribed thickness is deposited on the entire surface of the semiconductor substrate 1, and anisotropic etching is performed thereon to form an insulating layer 8 on the side walls of the gate electrodes 6a, 6b, 6c and 6d. Then, further using the gate electrodes 6a, 6b, 6c and 6d and the insulating layer 8 as masks, n type impurity ions are implanted onto the surface of the semiconductor substrate 1 to form highly concentrated impurity regions 7b and attain a state shown in FIG. 4B. Low concentrated impurity regions 7a and the highly concentrated impurity regions 7b constitute the source/drain regions 7 of an MOS (Metal Oxide Semiconductor) type field effect transistor.
A layer 9 of a metal having a high melting point such as tungsten, molybdenum, and titanium is formed entirely over the semiconductor substrate 1 (FIG. 1C).
The high melting point metal layer 9 is then patterned into a prescribed form to form a conductive interconnection layer 10 directly contacted by one of the source/drain regions 7 (FIG. 1D).
The gate electrodes 6a, 6b, 6c and 6d formed by the above described process constitute word lines of the DRAM memory cell, the conductive interconnection layer 10 forming bit lines.
After the formation of the conductive interconnection layer 10, memory cells are completed through the formation process of lower electrodes (storage nodes), dielectric layers, upper electrodes (cell plates), etc. The tops of the memory cells are schematically shown in FIG. 2. A cross section shown in FIG. 1D is taken along A--A in FIG. 2.
The DRAM memory cells formed undergoing the above process possesses the following problems.
A vertical section of the conductive interconnection layer 10 of the memory cells formed by the above conventional manufacturing process, i.e. a section taken along B--B shown in FIG. 2 is as shown in FIG. 3A. As can be seen from the FIG. 3A, depressions as shown by circles M, N are produced in the high melting point metal layer 9 or the conductive interconnection layer 10, because the gate electrodes 6b, 6c and 6d are widely spaced apart on the element isolation region 2. Such a depression produced in the high melting point metal layer 9 gives rise to the following problem. When patterning the high melting point metal layer to form the conductive interconnection layer 10, as shown in FIG. 3B, after a resist mask 13 is applied thereto, patterning is carried out by photolithography and etching to selectively etch away the high melting point metal layer 9. In the photolithography process of the resist mask 13, exposure is performed focusing at the vicinity of the lower plane of the resist mask 13, i.e. to the plane in the vicinity of the surface of the high melting point metal layer 9 (S plane indicated by chain double dotted line in FIG. 3B). Therefore, the depressions circled by M, N are out of focus of the exposure pattern in the surface of the high melting point metal layer 9, the contrast of the exposure pattern thereon being unclear. In developing the resist 13, the resist mask 13 in the vicinity of these depressions is therefore developed excessively to be thin in these places. Also in the conductive interconnection layer 10 after the high melting point metal layer 9 is selectively etched, thin portions are produced in these depressed portions, as shown in circles M, N in FIG. 3C, accordingly. These thin portions can cause degradation in conductivity in the conductive interconnection layer 10, resulting in defects such as disconnection in the extreme case.